DESCRIPTION

The IDT70V7599 is a high-speed 128Kx36 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM organized into 64 independent 2Kx36 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 2Kx36 memory block not already accessed by the other port.

Accesses by the ports into specific banks are controlled via the bank address pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V7599 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The dual chip enables also facilitate depth expansion.

The 70V7599 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply forthe core of the device(VDD) remains at 3.3V. Please refer also to the functional description on page 19.

APPLICATION

HIGH-SPEED x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH OR 2.5V INTERFACE

x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture ­ 64 independent x 36 banks ­ 4 megabits of memory on chip Bank access controlled via bank address pins High-speed data access ­ Commercial: 4.2ns (133MHz) (max.) ­ Industrial: (166MHz)/4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports ­ 5ns cycle time, 200MHz operation (14Gbps bandwidth) ­ Fast 3.4ns clock to data out 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs 200MHz ­ Data input, address, byte enable and control registers ­ Self-timed write allows fast cycle time Separate byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, 3.3V (±150mV) power supply for core LVTTL compatible, selectable 2.5V (±100mV) power supply for I/Os and control signals on each port Industrial temperature range +85°C) is available at 166MHz and 133MHz Available a 208-pin Plastic Quad Flatpack (PQFP), 208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball Grid Array (BGA) Supports JTAG features compliant with IEEE 1149.1

FEATURES

PL/FTL OPTL CLKL ADSL CNTENL REPEATL R/WL BE1L BE0L OEL PL/FTR OPTR CLKR ADSR CNTENR REPEATR R/WR BE1R BE0R OER

NOTE: 1. The Bank-Switchable dual-port uses a true SRAM core instead of the traditional dual-port SRAM core. As a result, it has unique operating characteristics. Please refer to the functional description on page 19 for details.

The is a high-speed 128Kx36 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM organized into 64 independent 2Kx36 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 2Kx36 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via the bank address pins under the user's direct control. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V7599 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The dual chip enables also facilitate depth expansion. The 70V7599 can support an operating voltage of either 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device(VDD) remains at 3.3V. Please refer also to the functional description on page 19.

NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking.

NOTES: 5626 drw 02d 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately x 1.4mm, with 1.0mm ball-pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking.

SPECIFICATION

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PICTURE

70V7599S166BCI8 image